/*
 * @ : Copyright (c) 2021 Phytium Information Technology, Inc. 
 *  
 * SPDX-License-Identifier: Apache-2.0.
 * 
 * @Date: 2021-06-29 15:13:47
 * @LastEditTime: 2021-09-02 11:00:53
 * @Description:  This files is for 
 * 
 * @Modify History: 
 *  Ver   Who        Date         Changes
 * ----- ------     --------    --------------------------------------
 */

#include "parameters.h"
#include "mmu.h"
#include "sdkconfig.h"

#ifdef CONFIG_TARGET_ARMV8_AARCH64

const struct arm_mmu_region mmu_regions[] = {
    MMU_REGION_FLAT_ENTRY("DEVICE_REGION",
                          0X00, 0x40000000,
                          MT_DEVICE_nGnRE | MT_RW | MT_NS),

    MMU_REGION_FLAT_ENTRY("PCIE_CONFIG_REGION",
                          0x40000000, 0x10000000,
                          MT_DEVICE_nGnRnE | MT_RW | MT_NS),

    MMU_REGION_FLAT_ENTRY("PCIE_REGION",
                          0x50000000, 0x30000000,
                          MT_DEVICE_nGnRE | MT_RW | MT_NS),

    MMU_REGION_FLAT_ENTRY("DDR_REGION",
                          0x80000000, 0x80000000,
                          MT_NORMAL | MT_RW | MT_NS),

    MMU_REGION_FLAT_ENTRY("PCIE_REGION",
                          0X1000000000, 0X1000000000,
                          MT_DEVICE_nGnRE | MT_RW | MT_NS),

    MMU_REGION_FLAT_ENTRY("DDR_REGION",
                          0X2000000000, 0X2000000000,
                          MT_NORMAL | MT_RW | MT_NS),
};

const uint32_t mmu_regions_size = ARRAY_SIZE(mmu_regions);

const struct arm_mmu_config mmu_config = {
    .num_regions = mmu_regions_size,
    .mmu_regions = mmu_regions,
};

#else

#define DDR_MEM (SHARED | AP_RW | DOMAIN0 | MEMWBWA | DESC_SEC)

struct mem_desc platform_mem_desc[] = {
    {0X00U,
     0X00U + 0x40000000U,
     0X00U,
     DEVICE_MEM},
    {0x40000000U,
     0x40000000U + 0x10000000U,
     0x40000000U,
     DEVICE_MEM},
    {0x50000000U,
     0x50000000U + 0x30000000U,
     0x50000000U,
     DEVICE_MEM},
    {0x80000000U,
     0xffffffffU,
     0x80000000U,
     DDR_MEM},
};

const u32 platform_mem_desc_size = sizeof(platform_mem_desc) / sizeof(platform_mem_desc[0]);

#endif

u32 ArmGicCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list)
{
    if (*cpu_mask == 0)
    {
        return 0;
    }

    *target_list = 0;
    *cluster_id = 0;

    if (*cpu_mask & 0x1)
    {
        *target_list = 1;
        *cpu_mask &= ~0x1;
    }
    else if (*cpu_mask & 0x2)
    {
        *cluster_id = 0X100;
        *target_list = 1;
        *cpu_mask &= ~0x2;
    }
    else if (*cpu_mask & 0xc)
    {
        *cluster_id = 0x200;
        if ((*cpu_mask & 0xc) == 0xc)
        {
            *target_list = 3;
        }
        else if ((*cpu_mask & 0x4))
        {
            *target_list = 1;
        }
        else
        {
            *target_list = 2;
        }
        *cpu_mask &= ~0xc;
    }
    else
    {
        *cpu_mask = 0;
        return 0;
    }

    return 1;
}

u64 GetMainCpuAffval(void)
{
    return 0;
}
